With the progress of artificial intelligence in recent years, how to apply artificial intelligence to chip design has become a hot topic in the semiconductor industry. With the development of relevant discussions, the entry point of artificial intelligence for the chip industry is increasingly focused on the EDA field, that is, how to use the powerful capabilities of artificial intelligence to help achieve chip design, verification and testing more efficiently.
Since artificial intelligence began to take off in 2016, there have been two landmark events, namely AlphaGO, which used reinforcement learning models and defeated Li Shishi, and ChatGPT, which was recently born out of large language model technology. Interestingly, these two technologies are precisely the key technologies for artificial intelligence to empower EDA.
At present, the EDA industry has officially entered the AI era, and we can expect to see more AI-powered EDAs emerge in the future.
The core technology behind artificial intelligence EDA
As mentioned earlier, the core technologies behind artificial intelligence-enabled EDA are two milestone technologies, namely reinforcement learning and large language models.
First of all, reinforcement learning is mainly used for optimization problems in EDA, including optimal placement and routing, and test/verification vector generation. The main challenge of this type of problem is that the parameter optimization space is huge, and it is not realistic to use brute force search to traverse all possible parameter combinations.
In addition to reinforcement learning, another key artificial intelligence technology is the large language model. Its main help to the EDA industry is that it can help engineers speed up code writing and reduce the chance of error. The Large Language Model (LLM) represented by ChatGPT can understand the needs of users expressed in natural language and generate natural language text that users can understand by learning rules from massive texts. The “natural language” here includes not only the language we usually speak, but also the programming language we write, including Verilog, which is commonly used in PCB design.
At present, the most successful LLM-based code writing aid tool is Github’s copilot, which can help users automatically complete the code (for example, after the user enters the first few characters of a line of code, copilot can predict what kind of code the user wants to write and prompt the user to complete it automatically) and automatically find bugs in the code. By fine-tuning the large language model on the existing RTL code, it is very hopeful that in the future there will be a tool to help chip design engineers quickly complete code writing, thereby greatly improving the efficiency of engineers.
How will artificial intelligence affect the work of engineers?
Artificial intelligence-driven EDA will undoubtedly further promote the development of the semiconductor industry, but will chip engineers be replaced by artificial intelligence? Generally speaking, just as the emergence of EDA did not replace the chip engineers of the year, the next-generation artificial intelligence-powered EDA is mainly a tool to improve efficiency and will not replace human engineers.
First, for chips, artificial intelligence EDA can mainly help to use large language models to improve the efficiency and quality of code writing for digital logic design. Therefore, there is no replacement relationship, but a more convenient tool is provided. For digital design engineers, the most essential job is to complete the circuit design, such as splitting a large system into multiple smaller functional modules, completing the function and interface definition of each module, and using code to implement these module.
At present, the artificial intelligence big language model mainly helps to complete the code, rather than writing the code directly. And even if artificial intelligence can automatically write codes in the future, it cannot replace the essential work of digital design engineers, which is to complete the definition and design of digital modules.
In the field of back-end design, artificial intelligence based on reinforcement learning has been able to greatly improve the efficiency and quality of layout and routing. At present, the design process of most chips is to first manually complete the high-level layout (floorplan) by engineers. After the estimated performance can be realized, the EDA tool will perform the next step of specific layout and wiring, and the engineers will verify and fine-tune. With the further improvement of the layout and routing efficiency and quality achieved by artificial intelligence, more and more work on floorplan may be handed over to EDA tools.
Increasingly, the engineer’s responsibility has become to provide reasonable constraints and optimization goals to the EDA tool, and to verify the quality of the design generated by the EDA tool. From this perspective, artificial intelligence may indeed do more work that engineers currently do manually, but this does not mean that artificial intelligence will replace these engineers, but it will allow these engineers to have additional responsibilities (that is, to provide tools with reasonable input and verification output), and improve the overall efficiency. For other placement and routing processes, artificial intelligence is more about a tool providing higher-quality and will not replace engineers.
In fact, artificial intelligence may provide more jobs in the chip industry. We know that artificial intelligence model training requires a large amount of data, and artificial intelligence models may require different fine-tuning training for different designs. Therefore, the chip design industry may need more engineers who can optimize artificial intelligence in a targeted manner.
Industry dynamics brought by artificial intelligence EDA
How will artificial intelligence further empower EDA in the future ?
First of all, the scale of chip design is getting larger and larger, and from another perspective, the search space for design is also getting larger and larger. In addition, as Moore’s Law is getting closer to the physical limit, the overall industry’s requirements for chip design PPA are getting higher and higher.
Therefore, the use of artificial intelligence to drive the further improvement of chip design performance will be more and more applied, and we believe that where the design complexity and degree of freedom are higher, artificial intelligence can play a greater role. These fields include advanced packaging, especially 3D packaging; and mobile chips, high-performance computing chips and other fields that have very high requirements for chip design PPA – This is why we see that companies such as Google and Nvidia, which focus on high-performance computing chips, have invested heavily in the field of artificial intelligence EDA.
In the future, we expect more such companies to use artificial intelligence EDA to improve PPA.