Wafer level packaging (WLP) is an advanced packaging technology. In recent years, with the development of more intelligent and sophisticated terminal applications such as mobile phones, computers, and AI, the demand for high computing power and highly integrated chips has increased. Therefore, advanced packaging technologies represented by Flip-Chip, 2.5D/3D IC package, wafer level package(WLP), and Sip are developing rapidly.
What is Wafer Level Package (WLP)
Wafer-level package, an advanced packaging, sometimes called WLCSP (wafer-level chip-scale package), is the smallest packaging technology available on the market today, but in fact, WLCSP is a more advanced Wafer Level Packaging. WLCSP (Wafer-Level Chip-Scale Package) is a packaging technology that combines wafer-level packaging (WLP) and chip-scale packaging (CSP).
Chip size packaging (CSP) refers to the packaging technology in which the area of the entire package does not exceed 120% of the total area of the silicon. This technique effectively facilitates the miniaturization of integrated circuits, but it is not suitable for server-class processor applications.
Wafer-level packaging (WLP) refers to packaging the wafer directly after the front-end process of the wafer is completed, and then cutting and separating it into a single chip. Compared with traditional IC packaging, the wafer is cut into a single chip and then packaged. WLP technology has obvious advantages in terms of packaging cost and production efficiency.
What is the process flow of wafer level packaging（WLP)
Step 1 : PI lithography
- Purpose:
1. Transfer the mask pattern to the wafer surface to obtain the CD openings required for the sputtering seed layer (UBM).
2. Generate a passivation layer as a protective film for subsequent processes. - Process principle: After coating PSPI on the surface of the wafer, UV exposure is carried out. After the passage of specific light, the properties of the colloid change, and then the required CD opening position is obtained through the development-curing process.
Step 2: Sputtering
- Purpose: To form a layer of metal films with different heights and types on the surface of the wafer by sputtering process and meet the process requirements, which is the seed layer (UBM) for the subsequent electroplating process .
- Process principle: According to the principle of physical vapor deposition, a high-purity metal material is placed in a vacuum chamber, and then ion beams, electron beams or high-energy particles are used to hit the surface of the metal material to cause sputtering to produce a large number of tiny metal particles , these particles are deposited on the wafer surface and gradually form a metal film.
Step 3: PR photolithography & electroplating
- Purpose: PR lithography is similar to the first layer of PI lithography. The main purpose of electroplating the copper layer above the UBM layer is to use it as a pad material for connecting chips and external circuit boards. This layer of copper material usually has good electrical conductivity and reliable soldering properties, which can effectively improve the connection reliability and durability of the chip. At the same time, the copper material can also improve the heat dissipation capability of the chip, thereby effectively reducing the temperature and power consumption of the chip.
- Process principle:
- PR photolithography: similar to the first layer of PI photolithography, but since the subsequent process is electroplating of the copper layer, the positive resist is replaced by the negative resist in the process, and there is no need to cure after exposure and development, but to remove the resist after electroplating operate;
- Electroplating: A layer of conductive paint, usually called solder, is applied on top of the UBM layer for the connection between the chip and the external circuit board. Then, the wafer is immersed in an electrolyte solution containing copper ions, and the solder is used as a cathode to reduce the copper ions on the surface of the solder to form a uniform copper layer.
Step 4: Plant the ball
- Purpose: Solder solder bump or copper pillar bump at the PCB pad, which is used as solder joint for subsequent Flip Chip process to connect substrate circuit.
- Process principle: Apply flux to the pad position, place solder balls at the corresponding position, and use reflow soldering to solder the solder ball to the pad position.
Step 5: Thinning & Scribing
- Purpose: According to the process requirements of specific products, the wafer is ground to the required thickness, and then the processed wafer is cut and separated into individual finished chips.
What are the advantages of WLP
1. High processing efficiency: wafer level package is manufactured in the form of wafer batch production process, with high processing efficiency
2. Small size: Compared with other packaging types, the wafer level package is also smaller in size, which is a good way to meet the needs of continuously reducing the size of portable electronic devices;
3. Good transmission performance: WLP effectively increases the bandwidth of data transmission and reduces signal loss, improving the speed and stability of data transmission;
4. Good heat dissipation performance: Since WLP has no plastic encapsulant or ceramic encapsulation like traditional packages, the heat dissipation effect is better;
5. Short production cycle: The chip design and packaging design of wafer level packaging can be considered and carried out at the same time, which will greatly improve the design efficiency, and the cycle will be greatly reduced in the whole process from chip manufacturing, packaging to product delivery to users.
What are types of advanced wafer level packaging technologies
1. Wafer Bumping Technology – Before cutting the wafer, solder balls (also called bumps) are formed or installed on the preset position of the wafer. Wafer bump is the key technology to realize the interconnection between chip and PCB or package substrate.
2. Fan-In wafer level packaging technology;
3. Fan-Out wafer-level packaging technology;
4. 2.5D wafer level packaging technology (including IPD);
5. 3D wafer level packaging technology (including IPD).
With the shrinking space of portable electronic products, increasing operating frequency and diversification of functional requirements, the number of chip input/output (I/O) signal interfaces has increased significantly, and the requirements for the precision of Bump Pitch & Ball Pitch are getting higher and higher. In this context, high-end wafer-level packaging technologies such as Fan-Out Wafer Level Packaging (FOWLP) and Hybrid Fan-In/Fan-Out Package have emerged.
Fan-Out Wafer Level Packaging technology
What is Fan-Out Wafer Level Packaging (FOWLP)
In traditional wafer-level package (WLP), the connection points (or I/O points) of the chip are directly on the surface of the chip. However, with the development of semiconductor technology, the size of the chip is getting smaller and smaller, while the number of I/O points is increasing, which makes it difficult to find enough space on the surface of the chip to place all the I/O points. It is getting more and more difficult.
FOWLP ( Fan-Out Wafer-Level Package) technology solves this problem. In FOWLP, the chip is first placed on a larger carrier (usually a wafer), and then a redistribution layer (RDL) connects the chip’s I/O points to the surface of the carrier. This allows I/O points to “fan out” beyond the boundaries of the chip, enabling higher I/O density and reducing package size while improving electrical performance.
What are the types of FOWLP process
FOWL has three process types: face-up, face-down, RDL-fist.
- Face-up
Face-up (or die up) Fan-Out Wafer-Level Packaging (FOWLP) is a common packaging process. In this process, semiconductor chips (die) are placed face-up on a carrier.
The following are the basic steps of the face-up
Face-up FOWLP process:
1. Chip placement: Semiconductor chips are placed face-up on a temporary carrier (usually a wafer).
2. Molding: The chip and carrier are encapsulated together using a molding material, usually epoxy. This step provides mechanical support while also protecting the chip.
3. Redistribution layer (RDL) fabrication: A redistribution layer is fabricated on the molding material by processes such as photolithography and electroplating. RDL can connect the I/O points of the chip to the surface of the carrier, thereby realizing the “fan-out” of the I/O points.
4. Solder ball attachment: Solder balls are formed on the RDL by a Ball Attach process. These solder balls can be used to connect the packaged chip to a circuit board.
5. De-carrier: The packaged chip is removed from the temporary carrier by a process called debonding.
- Face-down
Face-Down FOWLP is another common packaging process. In this process, semiconductor chips (die) are placed face down on a carrier.
The following are the basic steps of the face-down FOWLP process:
1. Chip placement;
2. Molding;
3. Carrier removal;
4. Redistribution layer (RDL) fabrication;
5. Solder ball attachment
- RDL-fist
RDL-first is a process flow of Fan-Out Wafer-Level Packaging (FOWLP). In this process, the redistribution layer (RDL) is fabricated before chip placement.
The following are the basic steps of the RDL-first FOWLP process:
1. RDL fabrication;
2. Chip placement;
3. Molding;
4. Carrier removal;
5. Solder ball attachment
Fan-in Wafer Level Packaging technology (FIWLP)
The difference between FOWLP and FIWLP is the size of the device. In the case of FIWLP, the packaged device size is the same as the die size, while in the FOWLP package, the packaged device size is larger than the die, similar to a traditional BGA package.
What is Fan-In Wafer Level Packageing (FIWLP)
Fan-In Wafer-Level Package (FIWLP) refers to the technology of packaging integrated circuits (ICs) at the wafer level, rather than the traditional process of dicing individual chips from wafers and assembling them into packages. FIWLP technology is an extension of the wafer fabrication process, using traditional fabrication processes and tools. Redistribution layers are used to connect device I/Os to solder ball locations on top of the chip surface.
FIWLP is a true chip scale packaging (CSP) technology because the final package is the same size as the die. Wafer-level package (WLP) technology differs from other ball grid array (BGA) and laminate-based CSPs because it does not require wire or interposer connections.
What are the process of FIWLP
1. Redistribution layer (RDL) fabrication: Fabricate a redistribution layer on dielectric materials through processes such as photolithography and electroplating.
2. Solder ball attachment: Solder balls are formed on the RDL by a solder ball attachment process. These solder balls can be used to connect the packaged chip to a circuit board.
3. Thinning
4. Cutting: cutting the wafer
5. Test
FIWLP vs FOWLP
- Number of pins: The package area of Fan – In WLP limits the number of pins, because all pins are located on the bottom of the chip. On the other hand, the design of FOWLP allows the pin layout to exceed the chip size, thereby increasing the pin count.
- Package size: Fan-In WLP typically enables smaller and lighter packages because it does not require an additional substrate or carrier. However, while the package size may be slightly larger, FOWLP enables more complex chip designs because it can accommodate more pins.
- Production cost: Fan-In WLP is usually more economical than FOWLP when producing in high volumes because of its relatively simple manufacturing process. However, if higher I/O pin counts or more complex designs are required, FOWLP may be a better choice.
Conclusion
With the continuous upgrading of electronic products, emerging markets such as smartphones, 5G, and AI have put forward higher requirements for packaging technology, making packaging technology develop in the direction of highly integrated, three-dimensional, and ultra-fine-pitch interconnection. Wafer-level packaging technology can reduce chip size, wiring length, solder ball pitch, etc., so it can improve the integration level of integrated circuits, processor speed, etc.
The advantages of reducing power consumption and improving reliability make wafer-level packaging meet the needs of the development of electronic products that are increasingly light, thin, small, and low-cost.
Wafer-level packaging is an advanced packaging technology that has developed rapidly with the development of more intelligent and sophisticated terminal applications such as mobile phones, computers, and AI. It mainly has the following advantages:
- Wafer-level packaging has
- High processing efficiency
- Small size
- Good transmission performance
- Good heat dissipation performance
- Short production cycle
Chip size packaging (CSP) refers to the packaging technology in which the area of the entire package does not exceed 120% of the total area of the silicon. While Wafer-level packaging (WLP) refers to packaging the wafer directly after the front-end process of the wafer is completed, and then cutting and separating it into a single chip.
Wafer level packaging technologies main include the following two types：
1. Fan-Out Wafer Level Packaging (FOWLP). In FOWLP, the chip is first placed on a larger carrier (usually a wafer), and then a redistribution layer (RDL) connects the chip's I/O points to the surface of the carrier.
2. Fan-In Wafer Level Packaging (FIWLP).FIWLP refers to the technology of packaging integrated circuits (ICs) at the wafer level, rather than the traditional process of dicing individual chips from wafers and assembling them into packages.
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