Vias are one of the critical components of multi-layer PCBs, which are used to achieve electrical connection among different layers of PCBs. In this article, there are some points you should pay attention to designing the PCB vias.
Type of vias
When it comes to functions, PCB vias can be divided into two categories. One is used as an electrical connection between layers. The other is to fix or position the device.
When it comes to the craft, vias are generally divided into three categories, that are blind via, buried via and through-hole via.
1. Blind via
Located on the top and bottom surfaces of the PCB, blind via is used to connect the surface circuit and the inner circuit. In addition, the depth of the hole usually does not exceed a certain ratio (aperture).
2. Buried via
It refers to the connection hole located in the inner layer of the PCB, which does not extend to the surface of the circuit board.
The above two types of holes are located in the inner layer of the circuit board. Before lamination, they are completed under the through-hole forming craft. Furthermore, several inner layers may be overlapped during the through-hole process.
3. Through-hole via
This kind of PCB vias runs through the entire circuit board, which can be used for internal interconnection or as a mounting location for components. Since the through hole is easier to make in the process and the cost is lower, most PCB manufacturers use it frequently instead of the other two types of vias.
The vias mentioned below, unless otherwise specified, are considered as through-hole via.
Size of vias
From a design point of view, PCB vias is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the vias.
Obviously, in high-speed, high-density PCB design, the designer always believes that the vias should be as small as possible. Then more wiring space can be left on the board. Moreover, the smaller the vias, the smaller the parasitic capacitance of itself, which is more suitable for high-speed circuits.
However, the reduction of the vias size also leads to an increase in cost. The size of the vias cannot be reduced without limitation as well. It is impacted by the technology of drilling and plating. The smaller of the via requires to take more time to drill and easier to make it deviate from the center position. When the depth of the via exceeds 6 times of the diameter of the drilled vias, it is difficult to ensure that the wall of the vias can be evenly plated with copper.
For example, if the thickness (through-hole depth) of a normal 6-layer PCB is 50Mil, the drilling diameter provided by the PCB manufacturer can only reach 8Mil under normal conditions.
With the development of laser drilling technology, the size of the drilled holes can also become smaller and smaller. Generally, the via with a diameter of less than or equal to 6Mil is called micro-via, which is often used in HDI (high-density interconnect) design. This technology allows vias to be directly placed on pads (Via-in-pad), which greatly improves circuit performance and saves wiring space.
Vias shows the discontinuous impedance breakpoints on the transmission line, which causes signal reflection. Generally, the equivalent impedance of the vias is about 12% lower than that of the transmission line. For example, the impedance of a 50-ohm transmission line generally decreases by 6 ohms when passing through the vias.
However, the reflection caused by the discontinuous impedance of the via hole is actually trivial. Its reflection coefficient is :
(44-50)/(44+50)=0.06
The problems caused by vias are more concentrated on the influence of parasitic capacitance and inductance.
The parasitic capacitance of Vias
The PCB via itself has a parasitic capacitance to the ground. If the diameter of the isolation via on the ground layer is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, then the parasitic capacitance of the via is approximate:
C=1.41εTD1/（D2-D1）
The main effect of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit.
For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, then we can approximate the via hole by the above formula.
The parasitic capacitance is rough:
C=1.41×4.4×0.050×0.020/（0.032-0.020）=0.517pF
The rise time variation caused by this part of capacitance is:
T10-90=2.2C（Z0/2）=2.2×0.517x（55/2）=31.28ps
From these values, we can discover that although the effect of slowing the rising delay caused by the parasitic capacitance of a single via is not obvious. But, if the vias are used multiple times in the wiring for inter-layer switching, we should pay attention to the variation of rise time.
The parasitic inductance of vias
Similarly, there is parasitic inductance as well as parasitic capacitance in the PCB vias. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of the via is often greater than the influence of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system.
We can simply calculate the approximate parasitic inductance of vias using the following formula:
L=5.08h［ln（4h/d）+1］
“L” refers to the inductance of the vias, “h” is the length of the via, and “d” is the diameter of the center drilled hole. It can be seen from the formula that the diameter of the via has little influence on the inductance, while the length of the via hole affects the inductance.
Still using the above example, the inductance of the vias can be calculated as:
L=5.08×0.050［ln（4×0.050/0.010）+1］=1.015nH
If the rise time of the signal is 1ns, then its equivalent impedance is:
XL=πL/T10-90=3.19Ω
Such impedance can no longer be ignored when there is a high-frequency current passing through. In particular, it should be noted that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer. In this way, the parasitic inductance of the vias will double.
Via design in high-speed PCB
Through the above analysis of the parasitic characteristics of vias, it’s clearly found that in high-speed PCB design, even simple vias often bring great negative effects to circuit design.
In order to reduce the adverse effects brought by the parasitic effects of vias, here are some points you can pay attention to.
1. Standing on cost and signal quality, select a vias with a reasonable size.
For example, for 6-10 layers of memory module PCB design, it is better to use 10/20Mil (drilling/pad) vias. For some high-density and small-sized boards, 8/18 mil vias can be tried using.
Under the current technical conditions, it is difficult to use smaller-sized vias. For power or ground vias, it can be considered to use a larger size to reduce impedance.
2. From the two formulas discussed above, it can be concluded that using a thinner PCB board is beneficial to reduce the two parasitic parameters of the vias.
3. The pins of the power supply and the ground should be drilled through vias nearby.
Besides, the lead between the via and the pin should be as shorter as possible. In this way, it enables to increase in the inductance. At the same time, the leads of power and ground should be as thick as possible to reduce impedance.
4. Try not to change the layer of the signal traces on the PCB. In other words, minimize unnecessary vias.
5. Place some grounded vias near the vias where the signal changes layers for providing a close loop for the signal. It is even possible to place a large number of redundant ground vias on the PCB.
The via model discussed above is the case where each layer has a pad. Sometimes, we can reduce or even remove the pads of some layers.
Especially in the case of a large vias density, it may cause a broken slot that isolates the circuit on the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider reducing the pad size of the via on the copper layer.
PCB vias is inlcuded three types that are the blind vias, buried vias and through-hole vias.
- Standing on cost and signal quality, select a vias with a reasonable size.
- using a thinner PCB board is beneficial to reduce the two parasitic parameters of the vias.
- The pins of the power supply and the ground should be drilled through vias nearby.
- Try not to change the layer of the signal traces on the PCB.
- Place some grounded vias near the vias where the signal changes layers for providing a close loop for the signal.
Conclusion
There are various PCB vias that we can choose to use in PCB design. PCB vias play a crucial role in creating electrical connections. Which types of vias we should use relies on the size and usage of PCBs. In addition, the capacities of buried vias, blind vias, or through-hole vias should be decided before your PCB layout design.
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