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Advanced packaging – from 2D, 3D to 4D packaging

Advanced packaging refers to the most advanced packaging forms and technologies at that time. At present, packaging with flip chip (Flip Chip, FC) structure, wafer level packaging (Water Level PackegeWLP), 2.5D packaging, 3D packaging, etc. are considered to belong to the category of advanced packaging.

Electronic integration technology is divided into three levels, on-chip integration, in-package integration, and PCB board-level integration. The representative technologies are SoC, SiP, and PCB (also called SoP or SoB).

Two important criteria for the classification of electronic integration technology: 1. Physical structure, 2. Electrical connection (electrical interconnection).

At present, according to the mainstream, advanced packaging can be divided into three types: 2D packaging, 2.5D packaging, and 3D packaging.

Table of Contents

2D packaging

One of the advanced packaging forms is 2D packaging, which refers to the integration method of mounting all chips and passive components horizontally on the surface of the substrate. 2D packaging includes technologies such as FOWLP and FOPLP.

Physical structure: All chips and passive components are installed on the substrate plane, the chips and passive components are in direct contact with the XY plane, and the wiring and vias on the substrate are located below the XY plane. 

Electrical connections: all need to pass through the substrate (except for a few bond points directly connected by bond wires).

TSMC’s InFO

TSMC's InFO
TSMC’s InFO

InFO technology developed by TSMC in 2017. InFO technology is similar to the Fan-out of most packaging factories. It can be understood as the integration of multiple chip Fan-out processes. The main difference is that the silicon interposer is removed and some RDL layers are used for serial connection (The A10 processor in the iPhone 7 launched in 2016 uses TSMC’s 16nm FinFET process and InFO technology).

Additionally, there is a 2D+ integration

2D+ integration refers to the traditional integration of chip stacks connected by bonding wires. Some people may ask, isn’t chip stacking just 3D, why should it be defined as 2D+integration?

Mainly based on the following two reasons:

1) 3D integration currently refers to the integration through 3D TSV to a large extent. In order to avoid conceptual confusion, we define this traditional chip stacking as 2D+ integration;

2) Although the physical structure is 3D, its electrical interconnection needs to pass through the substrate, that is, it is first bonded to the substrate through the bonding wire, and then electrically interconnected on the substrate. This is the same as 2D integration. The improvement over 2D integration is the structural stacking, which can save packaging space, so it is called 2D+ integration.

Physical structure: All chips and passive devices are located above the XY plane, some chips do not directly contact the substrate, and the wiring and vias on the substrate are located below the XY plane.

Electrical connection: all need to pass through the substrate (except for a very few bonding points that are directly connected by bonding wires).

2.5D package

2.5D packaging is also a kind of advanced packaging. It usually refers to both 2D and some 3D features. Representative technologies include Intel’s EMIB, TSMC’s CoWoS, and Samsung’s I-Cube.

Physical structure: All chips and passive devices are above the XY plane, at least some chips and passive devices are installed on the interposer. There are interposer wiring and vias above the XY plane, and substrate wiring and vias below the XY plane.

Electrical connection: The interposer can provide the electrical connection of the chip on the interposer.

The key to 2.5D integration lies in the interposer. Generally, there are several situations, 1) whether the interposer uses a silicon interposer, 2) whether the interposer uses TSV, and 3) adopts an interposer made of other types of materials; On the interposer board, we call the vias passing through the interposer TSV, and on the glass interposer board, we call it TGV .

The integration of silicon interposer with TSV is the most common 2.5D integration technology. The chip is usually connected to the interposer through MicroBump. The silicon substrate as the interposer is connected to the substrate by Bump. The surface of the silicon substrate is wired through RDL, and the TSV is used as a channel for electrically connecting the upper and lower surfaces of the silicon substrate. This 2.5D integration is suitable for situations where the chip scale is relatively large and the pin density is high. The chip is generally installed on the silicon substrate in the form of a FlipChip.

2.5D integration with TSV
2.5D integration with TSV

The structure of 2.5D integration without TSV in the silicon interposer is generally shown in the figure below. There is a large bare chip directly mounted on the substrate. The connection between the chip and the substrate can be done by Bond Wire or Flip Chip. Due to the large area above the large chip, multiple smaller bare chips can be installed, but the small chip cannot be directly connected to the substrate, so an interposer needs to be inserted to install multiple bare chips above the interposer.

2.5D integration without TSV
2.5D integration without TSV

There is RDL wiring on the interposer, which can lead the signal of the chip to the edge of the interposer, and then connect to the substrate through Bond Wire. This type of interposer usually does not require TSV, and only needs to be electrically interconnected through the wiring on the upper surface of the Interposer. The Interposer uses Bond Wire to connect to the package substrate.

Intel’s EMIB

The concept is similar to 2.5D packaging, but the difference from traditional 2.5D packaging is that there is no TSV. It is also for this reason that EMIB technology has the advantages of normal packaging yield, no additional process and simple design.

Intel's EMIB
Intel’s EMIB

TSMC’s CoWoS Technology

TSMC’s CoWoS technology is also a 2.5D packaging technology. According to the different interposers, it can be divided into three categories. One is that CoWoS_S(uses Si substrate as the interposer), the other is that CoWoS_R (uses RDL as the interposer), and the third is that CoWoS_L (uses chiplets (Chiplet) and RDL as the interposer).

TSMC's CoWoS Technology
TSMC’s CoWoS Technology

Samsung’s I-Cube

Samsung's I-Cube
Samsung’s I-Cube

Samsung’s advanced packaging includes four solutions: I-Cube, X-Cube, R-Cube and H-Cube. Among them, Samsung’s I-Cube also belongs to the 2.5D package.

3D packaging

The main difference between 3D packaging and 2.5D packaging is: 2.5D packaging is wiring and drilling on the Interposer, while 3D packaging is directly drilling and wiring on the chip to electrically connect the upper and lower chips. 3D integration is currently largely specific to integration via 3D TSVs.

Physical structure: All chips and passive devices are located above the XY plane, and the chips are stacked together. There are TSVs passing through the chip above the XY plane, and there are substrate wiring and vias below the XY plane.

Electrical connection: directly connect the chip electrically through TSV and RDL

3D integration is mostly applied in the same kind of chip stacking. Multiple identical chips are vertically stacked together and interconnected through TSVs passing through the chip stack, as shown in the figure below. Similar chip integration is mostly used in memory integration, such as DRAM Stack, FLASH Stack, etc.

3D integration of similar chips
3D integration of similar chips

In the 3D integration of different types of chips, two different chips are generally stacked vertically, electrically connected together through TSV, and interconnected with the underlying substrate. Sometimes it is necessary to make RDL on the surface of the chip to connect the upper and lower TSVs.

3D integration of different types of chips
3D integration of different types of chips

TSMC’s SoIC Technology

TSMC's SoIC Technology
TSMC’s SoIC Technology

TSMC’s SoIC technology belongs to 3D packaging and is a wafer-on-wafer bonding technology. SoIC technology uses TSV technology, which can achieve a non-bump bonding structure and integrate many adjacent chips of different natures.

SoIC technology integrates homogeneous and heterogeneous chiplets into a single SoC-like chip with smaller size and thinner form factor, which can be monolithically integrated into advanced WLSI (aka CoWoS and InFO). From the outside, the newly integrated chip looks like a general-purpose SoC chip, but embeds the required heterogeneous integration functions.

Intel’s Foveros Technology

Intel's Foveros Technology
Intel’s Foveros Technology

From the perspective of the structure of 3D Foveros, the bottom is the packaging substrate, and a bottom chip is placed on it, which acts as an active intermediary layer. There are a large number of TSV 3D through-silicon vias in the interposer, which are responsible for connecting the upper and lower solder bumps, allowing the upper chip and module to communicate with other parts of the system.

Samsung’s X-Cube 3D packaging technology

Samsung's X-Cube 3D packaging technology
Samsung’s X-Cube 3D packaging technology

Using the TSV process, Samsung’s X-Cube test chip has been able to stack the SRAM layer on top of the logic layer and interconnect it through TSV. The process is their own 7nm EUV process.

4D integration

Physical structure: multiple substrates are installed in a non-parallel manner, and components are installed on each substrate, and the installation methods of components are diversified.

Electrical connection: The substrates are connected by flexible PCB or soldering, and the electrical connections of the chips on the substrate are diversified.

4D integration
4D integration

The definition of 4D integration is mainly about the orientation and interconnection of multiple substrates, so 4D integration also includes 2D, 2D+, 2.5D, and 3D integration methods.

Conclusion

Advanced packaging plays a more important role in the process of improving chip integration, electrical connection and performance optimization. According to estimates by Yole Development, the global advanced packaging market has reached US$30 billion in 2020, and is expected to reach US$47.5 billion in 2026, with a CAGR of 8%. In 2026, advanced packaging will exceed 50% of the total packaging market.

FAQ

2D packaging refers to the integration method of mounting all chips and passive components horizontally on the surface of the substrate. 2D packaging includes technologies such as FOWLP and FOPLP.

3D packaging is directly drilling and wiring on the chip to electrically connect the upper and lower chips.

The definition of 4D integration is mainly about the orientation and interconnection of multiple substrates, so 4D integration also includes 2D, 2D+, 2.5D, and 3D integration methods.

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