Advanced packaging refers to the most advanced packaging forms and technologies at that time. At present, packaging with flip chip (Flip Chip, FC) structure, wafer level packaging (Water Level PackegeWLP), 2.5D packaging, 3D packaging, etc. are considered to belong to the category of advanced packaging.
Electronic integration technology is divided into three levels, on-chip integration, in-package integration, and PCB board-level integration. The representative technologies are SoC, SiP, and PCB (also called SoP or SoB).
Two important criteria for the classification of electronic integration technology: 1. Physical structure, 2. Electrical connection (electrical interconnection).
What is Advanced Semiconductor Packaging?
Advanced semiconductor packaging refers to the technology and methods used to package and integrate semiconductor devices (chips or ICs) into more complex and efficient structures beyond traditional packaging techniques. Here’s a comprehensive look into this innovative field:
Definition and Purpose:
Definition: Advanced semiconductor packaging involves techniques that go beyond basic chip encapsulation to enhance performance, reduce size, improve reliability, and enable new functionalities.
Purpose: It aims to meet the increasing demands for smaller, faster, and more power-efficient electronic devices. Advanced packaging techniques enable higher levels of integration, better thermal management, and improved electrical performance.
Types of Advanced Packaging:
System-in-Package (SiP): SiP integrates multiple chips (such as processors, memory, and sensors) into a single package. It allows different functional blocks to be combined in a compact form factor, reducing the overall footprint and enhancing performance.
3D Packaging: Also known as stacked die or vertical integration, 3D packaging involves stacking multiple semiconductor layers vertically. This technique reduces interconnect lengths, improves signal integrity, and increases packaging density.
Fan-Out Wafer-Level Packaging (FOWLP): FOWLP redistributes the connection points (I/Os) from the chip’s periphery to the package’s surface, enabling more I/Os and reducing package size. It is used in mobile devices and high-performance applications.
Embedded Die Packaging: In this approach, semiconductor dies are embedded within the substrate or PCB (Printed Circuit Board), enhancing thermal performance and reducing the electrical path lengths.
Wafer-Level Packaging (WLP): WLP involves packaging semiconductor devices at the wafer level before they are separated into individual chips. This reduces manufacturing costs and enables higher interconnect densities.
Benefits:
Miniaturization: Advanced packaging techniques allow for smaller and thinner packages, enabling compact and portable electronic devices.
Performance: Improved electrical and thermal characteristics lead to faster data transfer rates, reduced power consumption, and enhanced overall system performance.
Integration: Integration of multiple functions into a single package simplifies system design, reduces component count, and lowers system complexity.
Reliability: Enhanced thermal management and robust interconnects improve device reliability and longevity.
Applications:
Consumer Electronics: Smartphones, tablets, wearables, and IoT devices benefit from advanced packaging techniques to achieve compact designs with high performance and efficiency.
Computing: Advanced packaging supports high-performance computing applications such as servers, data centers, and AI accelerators by enabling dense integration and efficient thermal management.
Automotive: Advanced packaging ensures reliability and durability in harsh automotive environments while supporting features like advanced driver assistance systems (ADAS) and infotainment systems.
Advanced semiconductor packaging plays a crucial role in enabling the development of smaller, faster, and more efficient electronic devices across various industries. It represents a continuous evolution in semiconductor technology aimed at meeting the demands of next-generation electronics and applications.
Advantages of Advanced Semiconductor Packaging
Advanced semiconductor packaging offers several significant advantages over traditional packaging methods, driving innovation and enhancing the performance of electronic devices. Here’s a user-friendly exploration of these benefits:
Miniaturization and Size Reduction:
Advanced packaging techniques such as System-in-Package (SiP) and 3D packaging enable the integration of multiple chips and components into a smaller form factor.
This miniaturization allows manufacturers to create thinner and lighter devices, facilitating the development of sleeker smartphones, wearables, and other portable electronics.
Improved Performance:
Enhanced electrical and thermal characteristics of advanced packaging methods contribute to improved overall performance of semiconductor devices.
Shorter interconnect lengths in 3D packaging reduce signal delay and improve signal integrity, enabling faster data transfer rates and lower power consumption.
Better thermal management capabilities prevent overheating, thereby maintaining consistent performance and extending the lifespan of electronic components.
Higher Integration Density:
Advanced packaging techniques support higher levels of integration by stacking multiple semiconductor layers or embedding dies within substrates.
This denser integration reduces the footprint of electronic systems, increases functionality, and simplifies system design by reducing the number of external components.
Enhanced Reliability:
Robust interconnect technologies and improved thermal dissipation in advanced packaging enhance the reliability and durability of semiconductor devices.
Advanced packaging mitigates issues such as signal degradation, electromigration, and mechanical stress, ensuring consistent operation in demanding environments.
Cost Efficiency:
While initial development costs for advanced packaging may be higher, these techniques often lead to cost savings in manufacturing and assembly.
Wafer-level packaging (WLP) and fan-out wafer-level packaging (FOWLP) reduce material waste and assembly steps, lowering overall production costs compared to traditional methods.
Versatility and Customization:
Advanced packaging allows for greater flexibility in designing complex electronic systems tailored to specific applications.
System designers can mix and match different types of chips and components within a single package, optimizing performance and functionality for diverse market needs.
Applications Across Industries:
Advanced semiconductor packaging benefits various industries including consumer electronics, automotive, telecommunications, and healthcare.
It supports the development of cutting-edge technologies such as 5G networks, AI-enabled devices, autonomous vehicles, and medical diagnostic tools.
Advanced semiconductor packaging plays a pivotal role in advancing the capabilities of modern electronic devices by offering size reduction, improved performance, higher integration density, enhanced reliability, cost efficiency, versatility, and customization options. These advantages drive innovation and enable the development of next-generation electronics across multiple sectors.
Advanced packaging components and technologies
Advanced packaging components and technologies encompass a range of innovative approaches that enhance the performance, size, and functionality of semiconductor devices. Here’s a detailed exploration of these components and technologies in a clear and accessible manner:
System-in-Package (SiP):
Definition: SiP integrates multiple chips or functional blocks into a single package, enabling different technologies (such as logic, memory, and RF) to coexist within a compact form factor.
Advantages: SiP allows for improved performance by reducing interconnect lengths, which enhances signal integrity and minimizes power consumption. It also facilitates faster data processing by enabling concurrent operation of diverse functionalities.
3D Packaging:
Definition: Also known as stacked-die packaging, 3D packaging involves vertically stacking multiple semiconductor layers.
Advantages: This approach reduces the footprint of devices while increasing integration density. Shorter interconnects between stacked layers improve electrical performance, enabling higher bandwidth and faster data transfer rates. Additionally, 3D packaging enhances thermal management by enabling efficient heat dissipation through multiple layers.
Fan-Out Wafer-Level Packaging (FOWLP):
Definition: FOWLP redistributes the I/Os from the chip’s periphery to the package’s surface, allowing for a compact design with increased I/O density.
Advantages: FOWLP reduces package size and enhances electrical performance by minimizing interconnect lengths. It supports heterogeneous integration by enabling the integration of different technologies (such as logic, memory, and sensors) on the same package.
Embedded Die Packaging:
Definition: In embedded die packaging, semiconductor dies are embedded within the substrate or PCB.
Advantages: This approach enhances thermal dissipation by integrating heat-spreading materials within the package. It also reduces the electrical path length between components, thereby improving signal integrity and reducing electromagnetic interference (EMI).
Wafer-Level Packaging (WLP):
Definition: WLP involves packaging semiconductor devices at the wafer level before they are separated into individual chips.
Advantages: WLP reduces manufacturing costs by eliminating the need for traditional lead frames or interposers. It also enables higher interconnect densities and supports the development of ultra-thin and flexible electronic devices.
Advanced Interconnect Technologies:
Definition: Advanced interconnect technologies include through-silicon vias (TSVs), microbumps, and fine-pitch interconnects.
Advantages: These technologies facilitate dense integration and high-bandwidth communication between chips or layers within a package. TSVs, for example, enable vertical connections through the silicon substrate, reducing signal delay and enhancing overall device performance.
Materials and Manufacturing Processes:
Definition: Advanced packaging utilizes specialized materials (such as low-k dielectrics and metal alloys) and advanced manufacturing processes (such as laser ablation and thin-film deposition).
Advantages: These materials and processes enable precise control over package dimensions, electrical properties, and thermal characteristics. They also support the development of customized packaging solutions for specific applications in industries ranging from consumer electronics to automotive and aerospace.
Advanced packaging components and technologies play a crucial role in enhancing the performance, functionality, and reliability of semiconductor devices. By leveraging innovative approaches such as SiP, 3D packaging, FOWLP, and advanced interconnect technologies, manufacturers can meet the evolving demands for smaller, faster, and more efficient electronic products across various industries. These advancements drive innovation and enable the development of next-generation technologies that shape our digital future.
At present, according to the mainstream, advanced packaging can be divided into three types: 2D packaging, 2.5D packaging, and 3D packaging.
2D packaging
One of the advanced packaging forms is 2D packaging, which refers to the integration method of mounting all chips and passive components horizontally on the surface of the substrate. 2D packaging includes technologies such as FOWLP and FOPLP.
Physical structure: All chips and passive components are installed on the substrate plane, the chips and passive components are in direct contact with the XY plane, and the wiring and vias on the substrate are located below the XY plane.
Electrical connections: all need to pass through the substrate (except for a few bond points directly connected by bond wires).
TSMC’s InFO
InFO technology developed by TSMC in 2017. InFO technology is similar to the Fan-out of most packaging factories. It can be understood as the integration of multiple chip Fan-out processes. The main difference is that the silicon interposer is removed and some RDL layers are used for serial connection (The A10 processor in the iPhone 7 launched in 2016 uses TSMC’s 16nm FinFET process and InFO technology).
Additionally, there is a 2D+ integration
2D+ integration refers to the traditional integration of chip stacks connected by bonding wires. Some people may ask, isn’t chip stacking just 3D, why should it be defined as 2D+integration?
Mainly based on the following two reasons:
1) 3D integration currently refers to the integration through 3D TSV to a large extent. In order to avoid conceptual confusion, we define this traditional chip stacking as 2D+ integration;
2) Although the physical structure is 3D, its electrical interconnection needs to pass through the substrate, that is, it is first bonded to the substrate through the bonding wire, and then electrically interconnected on the substrate. This is the same as 2D integration. The improvement over 2D integration is the structural stacking, which can save packaging space, so it is called 2D+ integration.
Physical structure: All chips and passive devices are located above the XY plane, some chips do not directly contact the substrate, and the wiring and vias on the substrate are located below the XY plane.
Electrical connection: all need to pass through the substrate (except for a very few bonding points that are directly connected by bonding wires).
2.5D package
2.5D packaging is also a kind of advanced packaging. It usually refers to both 2D and some 3D features. Representative technologies include Intel’s EMIB, TSMC’s CoWoS, and Samsung’s I-Cube.
Physical structure: All chips and passive devices are above the XY plane, at least some chips and passive devices are installed on the interposer. There are interposer wiring and vias above the XY plane, and substrate wiring and vias below the XY plane.
Electrical connection: The interposer can provide the electrical connection of the chip on the interposer.
The key to 2.5D integration lies in the interposer. Generally, there are several situations, 1) whether the interposer uses a silicon interposer, 2) whether the interposer uses TSV, and 3) adopts an interposer made of other types of materials; On the interposer board, we call the vias passing through the interposer TSV, and on the glass interposer board, we call it TGV .
The integration of silicon interposer with TSV is the most common 2.5D integration technology. The chip is usually connected to the interposer through MicroBump. The silicon substrate as the interposer is connected to the substrate by Bump. The surface of the silicon substrate is wired through RDL, and the TSV is used as a channel for electrically connecting the upper and lower surfaces of the silicon substrate. This 2.5D integration is suitable for situations where the chip scale is relatively large and the pin density is high. The chip is generally installed on the silicon substrate in the form of a FlipChip.
The structure of 2.5D integration without TSV in the silicon interposer is generally shown in the figure below. There is a large bare chip directly mounted on the substrate. The connection between the chip and the substrate can be done by Bond Wire or Flip Chip. Due to the large area above the large chip, multiple smaller bare chips can be installed, but the small chip cannot be directly connected to the substrate, so an interposer needs to be inserted to install multiple bare chips above the interposer.
There is RDL wiring on the interposer, which can lead the signal of the chip to the edge of the interposer, and then connect to the substrate through Bond Wire. This type of interposer usually does not require TSV, and only needs to be electrically interconnected through the wiring on the upper surface of the Interposer. The Interposer uses Bond Wire to connect to the package substrate.
Intel’s EMIB
The concept is similar to 2.5D packaging, but the difference from traditional 2.5D packaging is that there is no TSV. It is also for this reason that EMIB technology has the advantages of normal packaging yield, no additional process and simple design.
TSMC’s CoWoS Technology
TSMC’s CoWoS technology is also a 2.5D packaging technology. According to the different interposers, it can be divided into three categories. One is that CoWoS_S(uses Si substrate as the interposer), the other is that CoWoS_R (uses RDL as the interposer), and the third is that CoWoS_L (uses chiplets (Chiplet) and RDL as the interposer).
Samsung’s I-Cube
Samsung’s advanced packaging includes four solutions: I-Cube, X-Cube, R-Cube and H-Cube. Among them, Samsung’s I-Cube also belongs to the 2.5D package.
3D packaging
The main difference between 3D packaging and 2.5D packaging is: 2.5D packaging is wiring and drilling on the Interposer, while 3D packaging is directly drilling and wiring on the chip to electrically connect the upper and lower chips. 3D integration is currently largely specific to integration via 3D TSVs.
Physical structure: All chips and passive devices are located above the XY plane, and the chips are stacked together. There are TSVs passing through the chip above the XY plane, and there are substrate wiring and vias below the XY plane.
Electrical connection: directly connect the chip electrically through TSV and RDL
3D integration is mostly applied in the same kind of chip stacking. Multiple identical chips are vertically stacked together and interconnected through TSVs passing through the chip stack, as shown in the figure below. Similar chip integration is mostly used in memory integration, such as DRAM Stack, FLASH Stack, etc.
In the 3D integration of different types of chips, two different chips are generally stacked vertically, electrically connected together through TSV, and interconnected with the underlying substrate. Sometimes it is necessary to make RDL on the surface of the chip to connect the upper and lower TSVs.
TSMC’s SoIC Technology
TSMC’s SoIC technology belongs to 3D packaging and is a wafer-on-wafer bonding technology. SoIC technology uses TSV technology, which can achieve a non-bump bonding structure and integrate many adjacent chips of different natures.
SoIC technology integrates homogeneous and heterogeneous chiplets into a single SoC-like chip with smaller size and thinner form factor, which can be monolithically integrated into advanced WLSI (aka CoWoS and InFO). From the outside, the newly integrated chip looks like a general-purpose SoC chip, but embeds the required heterogeneous integration functions.
Intel’s Foveros Technology
From the perspective of the structure of 3D Foveros, the bottom is the packaging substrate, and a bottom chip is placed on it, which acts as an active intermediary layer. There are a large number of TSV 3D through-silicon vias in the interposer, which are responsible for connecting the upper and lower solder bumps, allowing the upper chip and module to communicate with other parts of the system.
Samsung’s X-Cube 3D packaging technology
Using the TSV process, Samsung’s X-Cube test chip has been able to stack the SRAM layer on top of the logic layer and interconnect it through TSV. The process is their own 7nm EUV process.
4D integration
Physical structure: multiple substrates are installed in a non-parallel manner, and components are installed on each substrate, and the installation methods of components are diversified.
Electrical connection: The substrates are connected by flexible PCB or soldering, and the electrical connections of the chips on the substrate are diversified.
The definition of 4D integration is mainly about the orientation and interconnection of multiple substrates, so 4D integration also includes 2D, 2D+, 2.5D, and 3D integration methods.
Conclusion
Advanced packaging plays a more important role in the process of improving chip integration, electrical connection and performance optimization. According to estimates by Yole Development, the global advanced packaging market has reached US$30 billion in 2020, and is expected to reach US$47.5 billion in 2026, with a CAGR of 8%. In 2026, advanced packaging will exceed 50% of the total packaging market.
2D packaging refers to the integration method of mounting all chips and passive components horizontally on the surface of the substrate. 2D packaging includes technologies such as FOWLP and FOPLP.
3D packaging is directly drilling and wiring on the chip to electrically connect the upper and lower chips.
The definition of 4D integration is mainly about the orientation and interconnection of multiple substrates, so 4D integration also includes 2D, 2D+, 2.5D, and 3D integration methods.
Advanced packaging refers to the innovative techniques used to connect and integrate semiconductor chips within electronic devices. Unlike traditional methods, advanced packaging aims to enhance the performance, efficiency, and miniaturization of these devices.
This approach includes various methods like 3D stacking, where multiple layers of chips are stacked on top of each other to save space and improve speed. It also involves techniques like system-in-package (SiP), where different types of chips are combined into a single package to create a more compact and powerful system.
The main benefits of advanced packaging are increased processing power, reduced energy consumption, and smaller device sizes. This makes it crucial for the development of modern electronics, such as smartphones, wearables, and high-performance computing systems. Essentially, advanced packaging is all about making electronic devices faster, smaller, and more efficient.
Last updated on August 7th, 2024 at 11:17 am